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MC10EP17, MC100EP17 3.3V / 5V ECL Quad Differential Driver/Receiver
Description
The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. Inputs of unused gates can be left open and will not affect the operation of the rest of the device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100 Series contains temperature compensation.
Features
http://onsemi.com MARKING DIAGRAMS*
20 MCXXX EP17 ALYWG G 1
TSSOP-20 DT SUFFIX CASE 948E
20 1 SO-20 DW SUFFIX CASE 751D
20 MCXXXEP17 AWLYYWWG 1
* 220 ps Typical Propagation Delay * Maximum Frequency >3.0 GHz Typical * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V * * * * * *
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State Safety Clamp on Inputs Q Output Will Default LOW with Inputs Open or at VEE VBB Output Pb-Free Packages are Available*
20 1 QFN-20 MN SUFFIX CASE 485E XXXX EP17 ALYWG G
XXX = 10 or 100 A = Assembly Location L, = Assembly Lot WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 1 Publication Order Number: MC10EP17/D
(c) Semiconductor Components Industries, LLC, 2006
December, 2006 - Rev. 7
MC10EP17, MC100EP17
VCC 20 Q0 19 Q0 18 Q1 17 Q1 16 Q2 15 Q2 14 Q3 13 Q3 12 VEE 11
Table 1. PIN DESCRIPTION
PIN D[0:3]*, D[0:3]* Q[0:3], Q[0:3] VBB VCC VEE EP FUNCTION ECL Differential Data Inputs ECL Differential Data Outputs Reference Voltage Output Positive Supply Negative Supply Exposed Pad
1 VCC
2 D0
3 D0
4 D1
5 D1
6 D2
7 D2
8 D3
9 D3
10 VBB
* Pins will default LOW when left open.
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
Exposed Pad D0 20 VCC 19 VCC 18 Q0 17 Q0 16
D0 D1 D1 D2 D2
1 2 3 4 5 MC10/100EP17
15 14 13 12 11
Q1 Q1 Q2 Q2 Q3
6 NOTE:
7
8
9
10
D3 D3 VBB VEE Q3 The Exposed Pad (EP) on package bottom must be attached to a heat-sinking conduit. The Exposed Pad may only be electrically connected to VEE.
Figure 1. QFN-20 Pinout (Top View) Table 2. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 1 Level 1 N/A Value 75 kW N/A > 2 kV > 100 V > 2 kV Pb-Free Pkg Level 1 Level 3 Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC-20 TSSOP-20 QFN-20 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in 259 Devices
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MC10EP17, MC100EP17
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm Standard Board 20 TSSOP 20 TSSOP 20 TSSOP 20 SOIC 20 SOIC 20 SOIC QFN-20 QFN-20 QFN-20 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 140 100 23 to 41 90 60 30 to 35 47 33 18 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 4. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 4) Input HIGH Current Input LOW Current 0.5 Min 42 2165 1365 2090 365 1790 2.0 1890 Typ 50 2290 1490 Max 65 2415 1615 2415 1690 1990 3.3 150 0.5 Min 44 2230 1430 2155 1430 1855 2.0 1955 25C Typ 52 2355 1555 Max 66 2480 1680 2480 1755 2055 3.3 150 0.5 Min 46 2290 1490 2215 1490 1915 2.0 2015 85C Typ 54 2415 1615 Max 68 2540 1740 2540 1815 2115 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 3. All loading with 50 W to VCC - 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP17, MC100EP17
Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 7) Input HIGH Current Input LOW Current 0.5 Min 42 3865 3065 3790 3065 3490 2.0 3590 -40C Typ 50 3990 3190 Max 65 4115 3315 4115 3390 3690 5.0 150 0.5 Min 44 3930 3130 3855 3130 3555 2.0 3655 25C Typ 52 4055 3255 Max 66 4180 3380 4180 3455 3755 5.0 150 0.5 Min 46 3990 3190 3915 3190 3615 2.0 3715 85C Typ 54 4115 3315 Max 68 4240 3440 4240 3515 3815 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 6. All loading with 50 W to VCC - 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 6. 10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 8)
Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 9) Output LOW Voltage (Note 9) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 10) Input HIGH Current Input LOW Current 0.5 Min 42 -1135 -1935 -1210 -1935 -1510 -1410 VEE + 2.0 -40C Typ 50 -1010 -1810 Max 65 -885 -1685 -885 -1610 -1310 0.0 150 0.5 Min 44 -1070 -1870 -1145 -1870 -1445 -1345 VEE + 2.0 25C Typ 52 -945 -1745 Max 66 -820 -1620 -820 -1545 -1245 0.0 150 0.5 Min 46 -1010 -1810 -1085 -1810 -1385 -1285 VEE + 2.0 85C Typ 54 -885 -1685 Max 68 -760 -1560 -760 -1485 -1185 0.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. 9. All loading with 50 W to VCC - 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP17, MC100EP17
Table 7. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 13) Input HIGH Current Input LOW Current 0.5 Min 47 2155 1355 2075 1355 1775 2.0 1875 Typ 55 2280 1480 Max 63 2405 1605 2420 1675 1975 3.3 150 0.5 Min 50 2155 1355 2075 1355 1775 2.0 1875 25C Typ 58 2280 1480 Max 66 2405 1605 2420 1675 1975 3.3 150 0.5 Min 54 2155 1355 2075 1355 1775 2.0 1875 85C Typ 62 2280 1480 Max 70 2405 1605 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 12. All loading with 50 W to VCC - 2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 15) Output LOW Voltage (Note 15) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 16) Input HIGH Current Input LOW Current 0.5 Min 47 3855 3055 3775 3055 3475 2.0 3575 Typ 55 3980 3180 Max 63 4105 3305 4120 3375 3675 5.0 150 0.5 Min 50 3855 3055 3775 3055 3475 2.0 3575 25C Typ 58 3980 3180 Max 66 4105 3305 4120 3375 3675 5.0 150 0.5 Min 54 3855 3055 3775 3055 3475 2.0 3575 85C Typ 62 3980 3180 Max 70 4105 3305 4120 3375 3675 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 15. All loading with 50 W to VCC - 2.0 V. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP17, MC100EP17
Table 9. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 17)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 18) Output LOW Voltage (Note 18) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 19) Input HIGH Current Input LOW Current 0.5 Min 47 -1145 -1945 -1225 -1945 -1525 -1425 VEE + 2.0 Typ 55 -1020 -1820 Max 63 -895 -1695 -880 -1625 -1325 0.0 150 0.5 Min 50 -1145 -1945 -1225 -1945 -1525 -1425 VEE + 2.0 25C Typ 58 -1020 -1820 Max 66 -895 -1695 -880 -1625 -1325 0.0 150 0.5 Min 54 -1145 -1945 -1225 -1945 -1525 -1425 VEE + 2.0 85C Typ 62 -1020 -1820 Max 70 -895 -1695 -880 -1625 -1325 0.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 W to VCC - 2.0 V. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
-40C Symbol fmax tPLH, tPHL tJITTER Characteristic Maximum Frequency (Figure 2) Propagation Delay to Output Differential 10 Series 100 Series CLOCK Random Jitter (RMS) @ v 1.0 GHz @ v 1.5 GHz @ v 2.0 GHz @ v 2.5 GHz @ v 3.0 GHz Input Voltage Swing (Differential Configuration) Output Rise/Fall Times (20% - 80%) Q, Q 150 100 125 150 Min Typ >3 200 220 0.132 0.143 0.148 0.129 0.129 800 160 275 300 0.2 0.3 0.3 0.3 0.3 1200 220 150 100 150 180 Max Min 25C Typ >3 220 250 0.147 0.159 0.146 0.131 0.142 800 170 300 320 0.2 0.3 0.3 0.3 0.3 1200 230 150 120 200 200 Max Min 85C Typ >3 260 290 0.154 0.156 0.169 0.147 0.168 800 190 350 360 0.3 0.3 0.3 0.3 0.3 1200 250 Max Unit GHz ps
ps
VPP tr tf
mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V.
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MC10EP17, MC100EP17
800 700 VOUTpp (mV) 600 500 400 300 200 8 7 6 5 4 3 2 1 4000 5000 6000 JITTER OUT ps (RMS)
Driver Device Q Zo = 50 W 50 W 50 W D
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
EEEEEEEE EEEEEEEE
0 0 1000 2000 Q
100
(JITTER) 3000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Zo = 50 W
D Receiver Device
VTT VTT = VCC - 2.0 V
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EE EE
MC10EP17, MC100EP17
ORDERING INFORMATION
Device MC10EP17DT MC10EP17DTG MC10EP17DTR2 MC10EP17DTR2G MC10EP17DW MC10EP17DWG MC10EP17DWR2 MC10EP17DWR2G MC10EP17MNG MC10EP17MNTXG MC100EP17DT MC100EP17DTG MC100EP17DTR2 MC100EP17DTR2G MC100EP17DW MC100EP17DWG MC100EP17DWR2 MC100EP17DWR2G MC100EP17MNG MC100EP17MNTXG Package TSSOP-20 TSSOP-20 (Pb-Free) TSSOP-20 TSSOP-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) QFN-20 (Pb-Free) QFN-20 (Pb-Free) TSSOP-20 TSSOP-20 (Pb-Free) TSSOP-20 TSSOP-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) QFN-20 (Pb-Free) QFN-20 (Pb-Free) Shipping 75 Units / Rail 75 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 38 Units / Rail 38 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel 92 Units / Rail 3000 / Tape & Reel 75 Units / Rail 75 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 38 Units / Rail 38 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel 92 Units / Rail 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10EP17, MC100EP17
PACKAGE DIMENSIONS
TSSOP-20 CASE 948E-02 ISSUE C
20X
K REF
M
2X
L/2
20
11
J J1 B -U- N
L
PIN 1 IDENT 1 10
0.15 (0.006) T U
S
A -V-
N F DETAIL E -W-
DIM A B C D F G H J J1 K K1 L M
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
16X
16X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC10EP17, MC100EP17
PACKAGE DIMENSIONS
SO-20 WB CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
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10
L
MC10EP17, MC100EP17
PACKAGE DIMENSIONS
QFN-20 CASE 485E-01 ISSUE O
-X- A M N B 0.25 (0.010) T 0.25 (0.010) T R 0.08 (0.003) T E H L
6 5 10 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A B C D E F G H J K L M N P R MILLIMETERS MIN MAX 4.00 BSC 4.00 BSC 0.80 1.00 0.23 0.35 2.75 2.85 2.75 2.85 0.50 BSC 1.38 1.43 0.20 REF 0.00 0.05 0.35 0.45 2.00 BSC 2.00 BSC 1.38 1.43 0.60 0.80 INCHES MIN MAX 0.157 BSC 0.157 BSC 0.031 0.039 0.009 0.014 0.108 0.112 0.108 0.112 0.020 BSC 0.054 0.056 0.008 REF 0.000 0.002 0.014 0.018 0.079 BSC 0.079 BSC 0.054 0.056 0.024 0.031
-Y-
J C K -T-
SEATING PLANE
G
F
1 20 16 15
D
NOTE 3 M
P
0.10 (0.004)
TXY
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC10EP17/D

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